Arm Gesture Recognition for Human-Computer Interaction

Where: Université de Liège

When: 2010, 6 months

What: Master Thesis: Development and implementation of an algorithm for controlling a computer equipped with a stereo camera

Keywords: Image processing, computer vision, human-computer interaction, Stereo Vision, C++, OpenCV, CMake

This work presents an approach for human-computer interaction using a computer vision system based on a stereo camera. It is based on the depth information stereo heads are able to provide in order to track the user’s hand in space. The presented system is able to recover the position of the hand in the image plane as well as its distance from the camera. It is also able to identify if the user’s hand is closed or if the user is presenting his palm to the camera, in which case the system can recover the palm tilt. Those inputs are recovered in real-time and enable any user to control a typical mouse pointer simply by moving his/her fist in front of the camera, let him/her perform simple gestures that the system recognizes as clicks, page up/down and scroll up/down operations.

The actual system is using a stereo camera from Videre Designs (STH-MDCS2-9cm) and has been developed for Linux in C++ using the OpenCV as a back-end library to perform classic and well know tasks such as depth map computation or Kalman filtering.

The center core of the project is divided into two parts:

July 2012

Embedded software and electronics engineer

Where: Cossilys 21, S.A.

When: 2010, 6 months

What: Electrical schematic revision and firmware development for a USB I/O module.

Keywords: Embedded systems, Electrical systems, Microchip, MPLab, C, PIC18F Assembly, KiCad

Cossilys 21, S.A. is a French company developing and marketing video surveillance systems. In order for their system to actively react to various system alerts, they developed a first prototype of a USB controlled I/O electronic card. The system is featuring reed relays to drive external systems and electrically isolated digital inputs.

The goal of the internship was to debug the electrical circuit of the current prototype and update the circuit schematic. The second step was to develop and program the firmware for the Microchip PIC18F microcontroller powering the system. On top of managing the board I/Os, the firmware development also involved the management of the USB2 interface, both on the firmware side and on the computer side.

July 2012

Movement detection

Where: Université de Liège

When: 2009, 2 months

What: Detection of persons in a video stream.

Keywords: Image processing, computer vision, Video surveillance, C, OpenCV, CMake

Among a group of 3 master students, we had the task of developing an algorithm capable of recovering a video stream from an IP camera and process it so that persons within the field of view could be detected and tracked. The software was developed for Linux using C and the OpenCV library.

This project was decomposed in 3 major parts:

July 2012

Implementation of an OVM Based Advanced Functional Testbench for a Mixed-Signal A/D Converter

Where: Ecole Polytechnique Fédérale de Lausanne (EPFL) - Semtech Inc.

When: 2009, 4 months

What: Master Thesis: Develop a functional verification environment for Semtech’s RTL model of the SX8724 chip

Keywords: HDL Verification, functional Verification, SystemVerilog, QuestaSim, OVM

Semtech Inc. developed a medium-complexity mixed-signal zooming A/D converter with a small custom 12-bit processor and an I2C interface. It is a data acquisition system based on the ZoomingADCTM technology. It directly connects most types of miniature sensors with a general purpose microcontroller. So far, the design and the verification have been done using the VHDL language. However, this approach reached its limits with the complexity of the design and of the stimulus that are required to test it. Higher modeling abstraction levels, better means to express specifications and properties, and better means to measure performances are required. Also, the verification of mixed-signal designs needs to verify continuous- time properties that cannot be easily specified.

The goal of this project was to develop a functional verification environment for Semtech's RTL model of their SX8724 product. The verification environment is implemented using the SystemVerilog language and is compliant to the Open Verification methodology 2.0 specification. The verification environment was developed and validated using the Questa advanced verification platform from Mentor Graphics.

Existing VHDL testbenches were replaced with an OVM class-based environment that define a new verification environment targeted at complex mixed-signal systems. The new testbench environment heavily leverages object oriented programming techniques available in SystemVerilog and advance functional verification (AFV) methods such as SystemVerilog assertions (SVA), functional coverage, constraint random stimuli and testbench automation. The new approach was then be compared to the previous one using VHDL-based testbenches.

July 2012

Research assistant

Where: Ecole Polytechnique Fédérale de Lausanne (EPFL) - LSM

When: 2008, 3 months

What: Semi-custom IC design using the LEON3 softcore combined with specific SRAM IP.

Keywords: IC design, LEON3 processor, VHDL, Design Compiler, Cadence First Encounter, Bash Scripting

This project was planned for a 3 months summmer internship in the Microelectronic Systems Laboratory (LSM) at EPFL. The goal was the development of a library of Bash scripts automating the integration of a specific SRAM memory from Faraday-Tech for the LEON3 softcore processor from Gaisler, Inc.

A proof of concept of the scripts was done using Synopsis Design Compiler and Cadence First Encounter. As a result, a complete DRC free error layout of the LEON3 softcore integrating 4 SRAM blocs was realized using the UMC 0.18um CMOS technology. The resulting layout is 4.435mm2 and the maximum clock frequency is 175MHZ.

July 2012

Design of a Neurochip Off-Chip Support System using a FPGA

Where: Ecole polytechnique Fédérale de Lausanne (EPFL) - LSM

When: 2008, 3 months

What: Filtering interesting signals from a 100x100 bio-electrodes. VHDL signal processing.

Keywords: Signal processing, VHDL, Mentor Graphics ModelSim, FPGA, FPGA4U, Altera Cyclon II

The Microelectronic Systems Laboratory (LSM) at EPFL has been working a neurochip. This neurochip is composed of a microelectrode array (MEA) build on top of a CMOS chip. The array, composed of 100 by 100 electrodes, is designed to stimulate a neuronal culture grown on top of it and recover the electrical activity of the neurons. The data collected by the electrodes are sent out of the chip through 25 communication channels, each sending data at 64 Mbps.

The goal of this project was to design a signal processing algorithm to be put on a FPGA. This algorithm filters the data from the 25 channels, effectively sending relevant samples of the electrodes to a computer only. A working implementation was realized in pure VHDL and put on a FPGA4U board (Altera Cylon II) for demonstration purposes.

July 2012